The present invention relates to a data processing unit and, in particular, to a central processing unit (CPU) such as a microcomputer or microcontroller. Microcontrollers are well known in the art, and a large variety of such devices from low end devices (e.g., a 4/8-bit controller) to high end devices (e.g., a 32-bit controller) are available. Generally microprocessors are divided into two groups, namely general purpose processors, such as complex instruction set computers (CISC) or reduced instruction set computers (RISC), and special microprocessors designed for special purposes, such as digital signal processing processors (DSP).
RISC and CISC processors are usually processors having a plurality of registers or a register file and a single memory of any kind and size and therefore designed to process any kind of data. RISC and CISC processors are not limited for extensions but lack the high speed processing of DSP processors.
DSP processors usually have accumulators and a special memory limited in size. They are designed to calculate data very fast and precise, for example to process sampled signals. The memory is often split into a X-memory and a Y-memory to allow access to two different data in one cycle. This results in totally non orthogonal operations, severe restrictions on addressing modes and such a memory model is definitely not compiler friendly. If specific data is in the "wrong" memory, it has to loaded from X-memory to Y-memory or vice versa. The lack of a register file makes it also difficult to program such a processor in "C". Furthermore the narrow fixed instruction width makes it impossible to extend such an architecture.
Other systems use coprocessors to speed up operation. These coprocessors do not share any register of the main central processing unit (CPU). Thus, registers of the coprocessor have to be loaded by the CPU, which slows down operation speed significantly and limits usage of registers.